Work history
Sr Staff ASIC Verification Engineer
tags:
asic verification systemc
How would you describe your time at Not Disclosed?
Verification of ASICs in next generation Networking chip set
Staff ASIC Verification Engineer
tags:
fpga verification c++ verilog...
How would you describe your time at McData Corporation (now Bro...?
Developing next generation verification environment (C++/STL/Perl/SystemVerilog) for Routing and Extension products that connect fibre channel storage networks to wide area networks over IP
Re-architected the regression scripts for 3x speedup and better status reporting.
Updated FibreChannel and Gigabit Ethernet MACs test benches for revised inter chip communication protocol.... 
Manager
tags:
manager offshore eda architect
How would you describe your time at Sequence Design?
Managed the India infrastructure team to support the PhysicalStudio/Cooltime/Coolpower products. This group provides the basic features like net list, database, timing and optimization engine and electrical modeling for all Sequence products.
Responsible for the Electrical Modeler that provides advance characterization data to support voltage, timing and signal integrity analysis including cell capacitance, current waveform and voltage de-rating of delay.
Developed SPICE/NSIM interface for accurate dynamic rush current analysis for power gated designs.
Enhanced library model to support multiple rail dynamic voltage drop analysis.
Developed PrimeTime compatible collection commands and speeded them by a factor of 100
Developed physical optimization ECO routines for back annotation to Avanti flow....
Staff Test Architect
tags:
eda dft software development
How would you describe your time at LightSpeed Semiconductor?
Responsible for migrating proprietary Auto Test and Auto Bist technology from structured ASIC implementation to cell based ASIC design. Worked with library, cell and RTL designers to modify on-chip test logic and design flow for 100% functional test without DFT rules. Developed software for net listing and formatting test patterns....
Verification Lead
tags:
verification asic fpga c++ ve...
How would you describe your time at Riverstone Networks?
Led the development of the functional verification test environment software and test plan for the RS38K switch router hardware projects for the metro market.
Developed stand-alone test environment for MPLS chip set, including software model, stimulus generation, comparison and reporting.
Enhanced system simulation environment for verifying next generation of 4 Asics (GigE/OC MACs and PacketProcessor).
Implemented stand-alone verification environment for 3 FPGA based forwarding processor.
Developed Transaction Level Self Checking Test bench including BFMs, Monitors, Protocol Checkers, Data Integrity Checkers, golden functional model, directed and random stimulus generator, intelligent comparator and reporting etc.
Worked closely with software and hardware engineers to resolve specs and finalize test plan. (UNIX/C/C++/Verilog PLI/Solaris/Linux)...
Manager
tags:
manager emulation eda simulat...
How would you describe your time at Quickturn Design Systems (n...?
Led a team of 3-8 engineers directly and coordinated cross-functional teams to deliver a hardware verification system that brought in $10M/quarter for the company.
Led the compilation software development for a high performance cycle based simulation acceleration and emulation machine (Cobalt/Palladium).
Architected and implemented the compilation flow for mapping designs into the hardware.
Implemented net list optimizations to improve emulation capacity.
Worked with customers to make their emulation successful.
Handled project definition, staffing, development, porting and release co-ordination.
Developed kernel of the debug environment for emulation....
Staff Engineer
tags:
eda testability atpg diagnost...
How would you describe your time at CrossCheck Technology?
Co-architect and implementer of the second-generation proprietary on-chip testability software for ASIC designs.
Developed fault simulation, automatic test pattern generation and defect isolation software.
Education
Electrical Engineering
tags:
dft atpg reliability
How would you describe your time at Stanford University?
Study towards PhD in Reliability and Testing Group
Computer Engineering
How would you describe your time at University of Southern Cali...?
MS Computer Engineering
Design Automation and Testing
Electrical and Electronics Engineering
How would you describe your time at Indian Institute of Technol...?
B.Tech Electrical and Electronics Engineering
