Job Search Results for "Chip Tapeout" Jobs

Altera | San Jose, CA

Principal SOC Design Engineer Location: US-CA-San Jose Requisition ID: 2554 # of openings: 1 Description As a Principal SOC Design Engineer, you will be responsible for the Full Chip timing analysis and closure of Altera's next generation products. Working as part of a team, your job funct...

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Altera | San Jose, CA

Principal SOC Design Engineer Location: US-CA-San Jose Requisition ID: 2570 # of openings: 1 Description As a Principal Design Engineer, you will be responsible for the SOC design of Altera's next generation products. Working as part of a team, your job function includes: * Lead the SOC de...

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Apple | Santa Clara, CA

Requisition Number 15955688 Job title CPU Physical Integration Engineer Location Santa Clara Valley Country City State Job type Job description As a Full Chip Integration Engineer, you will be participating in the physical design, integration and verification of high performance processor proje...

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Broadcom Corporation | San Diego, CA

verification environments and test suites for full chip and block level with team members - Work closely... ASIC verification for a successful silicon tapeout...

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Immedia Semiconductor | Andover, MA

with successful tapeouts · Solid understanding of... in a fully compliant 1080p60 capable single chip decoder solution. Ratified in 2007, H.264 Scalable Video... ...

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Cadence Design Systems | Irvine, CA

a design from RTL to tapeout. Must have current US... customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs... ...

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TSMC | San Jose, CA

Responsibilities: Chip implementation. eCPU implementation and sign-off. Provide on-site chip... record in production tapeouts of multi-million gate... ...

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Northrop Grumman | Baltimore, MD

timing analysis, on chip variation timing analysis... design experience with at least 4 successful tapeouts of 10M gates or more; experience with 65nm or... ...

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Cadence Design Systems | San Jose, CA

with customers to understand their requirements to tapeout their designs. Tasks including but not limiting... Digital ICs , System-On-Chip devices, IP and complete... ...

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Fabless Semiconductor - Location / WiFi / Bluetooth | San Jose, CA

direct and implement chip level AMS (Analogue Mixed... maximizing chip level verification and consequently proactively finding and addressing chip level issues... ...

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