Research Assistant
tags:
perl
• synopsys primetime dc
• assembly
• asic design
• mentor graphic calibre icstation
• cadence design tool
• digital logic design
• c/c++
How would you describe your time at Oklahoma State Universtity,...?
* Conduct research on advanced computer arithmetic.
- Utilize PERL scripts to generate parameterized Verilog modules.
- Facilitate design flow using shell and Tcl scripting languages for synthesis (Synopsys Design Compiler), place & route (Cadence SoC Encounter) and simulation (Cadence NC-Verilog).
* Expand SCMOS standard-cell design flow for Mentor Graphics FreePDK project.
- Construct standard-cell libraries in IC Station compatible format and run place & route.
- Render Design For Test (DFT) flow with FastScan, DFTAdvisor.
* Adapted Synopsys SoC design flow for SRC/Synopsys FreePDK project.
- Converted Okstate SCMOS technology to Synopsys database through Milkyway.
- Performed place & route through Synopsys Recommended Astro Methodology (RAM).
- Compiled DRC rules for 45-nm technology and generated standard cells with Cadabra.
* Created High-Density SRAM/ROM in the form of highly reusable IP under TSMC 0.18 and AMI 0.5 processes.
- Utilized Cadence SKILL language to generate layout automatically.
- Provided timing files, Verilog descriptions and SPICE simulation files for the circuit characterization.... 
Electrical Engineering
tags:
digital logic design
• c/c++
• assembly
How would you describe your time at Illinois Institurte of Tech...?
* Developed the Neurotalk and USB interface.
- Integrated the transceiver and the interface to the analog Block-chip.
- Implemented the design as an ASIC with Verilog HDL and Tanner EDA software.
- Performed the post-synthesis verification and static timing analysis with ModelSim.
* Explored and realized state-of-the-art division algorithms and approximation methods....
