Michael Hughes

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fpga design • verilog vhdl • modelsim • synplicity synplify pro • xilinx virtex
fpga design • verilog vhdl • modelsim • synplicity synplify pro • xilinx virtex • altera stratix • fpga hardware software electr... • fpga programming • fpga verification c++ verilog... • xilinx ise • altera quartus • mentor cadence • ncsim vcs • rtl synthesis • matlab simulink • chipscope • synplicity identify • c/c++ • debussy • synthesizable testbench • rtl and gate-level verification • silicon validation • digital computer design • fpga hardware software electr...